The present invention relates to scrambling of data.
Switching activity from the digital outputs of an analog-to-digital converter (ADC) may couple into the analog signal path, resulting in spurs or other signal distortions, because the most significant bits are highly correlated with a digital signal.
Robert Jewett, Ken Poulton, Kuo-Chiang Hsieh, Joey Doernberg, “A 12 bit 128 MSample/s ADC with 0.05 LSB DNL”, IEEE International Solid-State Circuits Conference, 1997, Paper FA 8.4, p. 138 introduces XOR scrambling with a random signal to decorrelate the digital outputs from the analog input and thus convert the coupling power into broadband noise. The scrambling signal is provided as a separate signal for descrambling. When connecting accordingly scrambled 16 bit ADCs to a test device for testing a device under test (DUT), for instance a 93000 apparatus of Agilent Technologies, having a test processor with 8 bit wide vectors, the additional scrambling bit leads to inefficient sample sizes.
Such a decorrelation of transmitted digital signals with a random signal that logically processes the data bits according to an XOR logic and that is transmitted along with the randomized data as an additional signal introduces a random signal coming, for instance, from an LFSR (Linear Feedback Shift Register).
Random scrambling may allow to have improved spur suppression. Coupling power may be converted from spurs into broadband noise.
However, the random scrambling approach may necessitate an additional pin for carrying the random signal, and the implementation of an LFSR or a random signal generation unit may introduce additional noise so as to deteriorate the signal transmission quality.
U.S. Pat. No. 7,006,016 discloses a data encoding system for a data stream, which comprises a data dependent scrambler that receives the data stream including K m-bit symbols, that selects a seed based on the K m-bit symbols, that scrambles the K m-bit symbols using the seed and that outputs a codeword including the scrambled K m-bit symbols and the seed. A DC control module receives a plurality of the codewords from the data dependent scrambler, selectively inverts selected ones of the plurality of codewords to reduce a difference between a total number of zeroes and total number of ones in the plurality of codewords and outputs an encoded data stream.